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oki semiconductor fedsms81v26000-02 issue date: dec 15, 2004 ms81v26000 1,114,112-word 24-bit field memory 1/20 general description the oki ms81v26000 is a high performance 26-mbit, 1,100k 24-bit, field memory. it is especially designed for high-speed serial access applications such as hdtv s, conventional ntsc tvs, vtrs, digital movies and multi-media systems. ms81v26000 is a fram for wide or low end use in general commodity tvs and vtrs exclusively. ms81v26000 is not designed for the other use or high end use in medical systems, professional graphics systems which require long term pict ure storage, data storage systems and others. more than two ms81v26000s can be cascaded directly without any delay devices among the ms81v26000s. (cascading of ms81v26000 provides larger storage depth or a longer delay). each of the 24-bit planes has separate serial write and read ports. these employ independent control clocks to support asynchronous read and write op erations. different clock rates are also supported that allow alternate data rates between write and read data streams. the ms81v26000 provides high speed fifo, first-in first-out, operation without external refreshing: ms81v26000 refreshes its dram storage cells automatica lly, so that it appears fully static to the users. moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. internal conflicts of memory access and refr eshing operations are preven ted by special arbitration logic. the ms81v26000?s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. the delay length, number of read delay cloc ks between write and read, is determined by externally controlled write and read reset timings. additionally, the ms81v26000 has write mask function or input enable function (ie), and read-data skipping function or output enable function (oe) . the differences between write enable (we) and input enable (ie), and between read enable (re) and output enable (oe) ar e that we and re can stop serial write/read address increments, but ie and oe cannot stop the increment, when write/read clocking is continuously applied to ms81v26000. the input enable (ie) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. this faci litates data processing to display a ?picture in picture? on a tv screen.
feds81v26000-02 oki semiconductor ms81v26000 2/20 features ? single power supply: 3.3 v 0.3 v ? 1,114,112 words 24 bits ? fast fifo (first-in first-out) operation ? high speed asynchronous serial access read/write cycle time 12 ns access time 9 ns ? randomly accessible leading address ? variable length delay bit (350 to 1,114,112) ? write/read start address settable ? write mask function (input enable control) ? data skipping function (output enable control) ? self refresh (no refresh control is required) ? package options: 100-pin plastic tqfp (tqfp100-p-1414-0.50-k) (ms81v26000-xxtb) xx indicates speed rank. product family family access time (max.) cycle time (min.) package ms81v26000-12tb 9 ns 12 ns (83 mhz) 100-pin tqfp
feds81v26000-02 oki semiconductor ms81v26000 3/20 pin configuration (top view) pin name function swck serial write clock srck serial read clock we write enable re read enable ie input enable oe output enable rstw write reset clock rstr read reset clock wad write address input rad read address input d in 0 to 23 data input d out 0 to 23 data output v cc power supply (3.3 v) v ss ground (0 v) v cc q power supply for output v ss q ground for output nc no connection note: the same power supply voltage must be provided to every v cc pin and v cc q pin, and the same gnd voltage level must be provided to every v ss pin and v ss q pin. v ss di4 di5 di6 di7 v ss di8 di9 di10 di11 v ss v cc nc nc v ss v cc v ss q do11 do10 v cc q do9 do8 v ss q do7 do6 100-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v cc di3 di2 di1 di0 v ss wad ie we rstw v cc swc k v ss src k v cc rstr re oe rad v ss di12 di13 di14 di15 v cc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 v ss di16 di17 di18 di19 v ss di20 di21 di22 di23 v ss v cc nc nc v ss v cc v ss q do23 do22 v cc q do21 do20 v ss q do19 do18 v cc v cc q do5 do4 v ss q v ss do3 do2 v cc q do1 do0 v ss v ss q v cc do12 do13 v cc q do14 do15 v ss v ss q do16 do17 v cc q v cc
feds81v26000-02 oki semiconductor ms81v26000 4/20 block diagram refresh counter data-output buffer read data register x decode r (x 24 ) serial read controlle r (x 24 ) serial write controller data-input buffer read/write refresh timing generater do (x 24 ) oe re rstr srck di (x 24 ) ie we rstw swck 1 , 114 , 112 x 24 memor y arra y write data register rad wad
feds81v26000-02 oki semiconductor ms81v26000 5/20 pin description serial write clock: swck the swck latches the input data on chip when we is high , and also increments the internal write address pointer. data-in setup time tds, and hold time tdh are referenced to the rising edge of swck. write reset: rstw rstw is used to set the internal write address pointer. rstw setup and hold times are referenced to the rising edge of swck. the swck latches the write ad dress data (21bits serial lsb) from wad. write enable: we we is used for data write enable/disable control. we hi gh level enables the input, and we low level disables the input and holds the internal write address pointer. there are no we disable time (low) and we enable time (high) restrictions, because the ms81v26000 is in fully static operation as long as the power is on. note that we setup and hold times are referenced to the ri sing edge of swck. the latency for th e write operation control by we is 4. after write reset, we must remain low for more than 16 00 ns (tfwd). after write re set, the write operation at address 0 is started after a time twl form the cycle in which we is brought high. after write reset, we should be remained high for 2 cycles after driving we high first. input enable: ie ie is used to enable/disable writing into memory. ie hi gh level enables writing. the in ternal write address pointer is always incremented by cycling swck regardless of the ie level. note that ie setup and hold times are referenced to the rising edge of swck. the latency for the write operation control by ie is 4. write address input: wad these pins are used for write address input. data inputs: (di0-23) these pins are used for serial data inputs. write reset: rstw rstw is used to set the internal write address pointer. rstw setup and hold times are referenced to the rising edge of swck. the swck latches the write ad dress data (21bits serial lsb) from wad. data out: (do0-23) these pins are used for serial data outputs. serial read clock: srck data is shifted out of the data registers. it is triggered by the rising edge of srck when re is high during a read operation. the srck input increments the internal read address pointer when re is high. the three-state output buffer provides direct ttl compatibilit y (no pullup resistor required ). data out is the same polarity as data in. the output becomes valid after the access time in terval tac that begins with the rising edge of srck. *there are no output valid time restriction on ms81v26000. read reset: rstr rstr is used to set the internal read address pointer. rstr setup and hold times are referenced to the rising edge of srck. the swck latches the read address data (21bits serial lsb) from rad. read enable: re the function of re is to gate of the srck clock for incr ementing the read pointer. when re is high before the rising edge of srck, the read pointer is incremented. when re is low, the read pointer is not incremented. re setup times (trens and trdss) and re hold times (trenh and trdsh) are referenced to the rising edge of the srck clock.
feds81v26000-02 oki semiconductor ms81v26000 6/20 the latency for the read operation contro l by re is 4. after read reset, re must remain low for more than 1600 ns (tfrd). after read reset, the read data at address 0 is out put after a time trl from the cycle in which we is brought high. after read reset, re should be remained high for 2 cycles after driving re high first. output enable: oe oe is used to enable/disable the outputs. oe high level enables the outputs. the intern al read address pointer is always incremented by cycling srck regardless of the oe le vel. note that oe setup and hold times are referenced to the rising edge of srck. the latency fo r the read operation control by oe is 4. read address input: rad these pins are used for read address input.
feds81v26000-02 oki semiconductor ms81v26000 7/20 electrical characteristics absolute maximum ratings parameter symbol conditon rating unit power supply voltage v cc ta = 25 c ?0.5 to +4.6 v input output voltage v t at ta = 25 c, v ss ?0.5 to +4.6 v output current i os ta = 25 c 50 ma power dissipation p d ta = 25 c 1 w operating temperature t opr ? 0 to 70 c storage temperature t stg ? ?55 to +150 c recommended operating conditions parameter symbol min. typ max. unit power supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 v cc v cc + 0.3 v input low voltage v il ?0.3 0 +0.8 v dc characteristics parameter symbol cond ition min. max. unit input leakage current i li 0 < v i < v cc + 0.3 v, other pins test ed at v = 0 v ?10 +10 a output leakage current i lo 0 < v o < v cc ?10 +10 a output ?h? level voltage v oh i oh = ?2 ma 2.4 ? v output ?l? level voltage v ol i ol = 2 ma ? 0.4 v operating current i cc1 minimum cycle time, output open ? 200 ma standby current i cc2 input pin = v ih /v il ? 5 ma capacitance (v cc = 3.3 v 0.3 v, ta = 25 c, f = 1 mhz) parameter symbol max. unit input capacitance c i 6 pf output capacitance c o 7 pf
feds81v26000-02 oki semiconductor ms81v26000 8/20 ac characteristics (v cc = 3.3 v 0.3 v, ta = 0 to 70 c) ms81v26000-12 parameter symbol min. max. unit access time from srck t ac ? 9 ns d out hold time from srck t ddck 3 ? ns d out enable time from srck t deck 3 9 ns swck ?h? pulse width t wswh 4 ? ns swck ?l? pulse width t wswl 4 ? ns input data setup time t ds 3 ? ns input data hold time t dh 1 ? ns we enable setup time t wens 3 ? ns we enable hold time t wenh 1 ? ns we disable setup time t wdss 3 ? ns we disable hold time t wdsh 1 ? ns ie enable setup time t iens 3 ? ns ie enable hold time t ienh 1 ? ns ie disable setup time t idss 3 ? ns ie disable hold time t idsh 1 ? ns we ?h? pulse width t wweh 4 ? ns we ?l? pulse width t wwel 4 ? ns ie ?h? pulse width t wieh 4 ? ns ie ?l? pulse width t wiel 4 ? ns rstw setup time t rstws 3 ? ns rstw hold time t rstwh 1 ? ns srck ?h? pulse width t wsrh 4 ? ns srck ?l? pulse width t wsrl 4 ? ns re enable setup time t rens 3 ? ns re enable hold time t renh 1 ? ns re disable setup time t rdss 3 ? ns re disable hold time t rdsh 1 ? ns oe enable setup time t oens 3 ? ns oe enable hold time t oenh 1 ? ns oe disable setup time t odss 3 ? ns oe disable hold time t odsh 1 ? ns re ?h? pulse width t wreh 4 ? ns re ?l? pulse width t wrel 4 ? ns oe ?h? pulse width t woeh 4 ? ns oe ?l? pulse width t woel 4 ? ns rstr setup time t rstrs 3 ? ns rstr hold time t rstrh 1 ? ns swck cycle time t swc 12 ? ns srck cycle time t src 12 ? ns transition time (rise and fall) t t 1 5 ns
feds81v26000-02 oki semiconductor ms81v26000 9/20 ms81v26000-12 parameter symbol min. max. unit we ?l? period before w reset t lwe 4 ? clk re ?l? period before r reset t lre 4 ? clk re delay after reset t frd 1,600 ? ns we delay after reset t fwd 1,600 ? ns write address input period t wae 21 ? clk read address input period t rae 21 ? clk latency parameter symbol ms81v26000-12 unit write latency t wl 4 clk read latency t rl 4 clk we write control latency t wel 4 clk ie write control latency t iel 4 clk re read control latency t rel 4 clk oe read control latency t oel 4 clk ac characteristic measuring conditions output compare level 1.4 v output load 1 ttl + 30 pf input signal level 2.4 v/0.4 v input signal rise/fall time 1 ns input signal measuring reference level 1.4 v note: when transition time t t becomes 1 ns or more, the input signal reference levels for the parameter measurement are v ih (min.) and v il (max.).
feds81v26000-02 oki semiconductor ms81v26000 10/20 operation mode write operation cycle the write operation is controlled by four control signals, swck, rstw, we and ie. the write operation is accomplished by cycling swck, and holding we high afte r the write address pointer reset operation or rstw. rstw must be performed for internal circuit initializati on before write operation. we must be low before and after the reset cycle (t lwe + t wae + t fwd ). each write operation, which begins after rstw must cont ain at least 231 active write cycles, i.e., swck cycles while we and ie are high. settings of we and ie to the operation mode of write address pointer and data input. we ie internal write address pointer data input (latency 4) h h input h l incremented l x halted not input x indicates "don't care" read operation cycle the read operation is controlled by four control signals, srck, rstr, re, and oe. the read operation is accomplished by cycling srck, and holdin g both re and oe high after the read address pointer reset operation or rstr. each read operation, which begins af ter rstr, must contain at least 231 ac tive read cycles, i.e., srck cycles while re and oe are high. re must be low before and after the reset cycle (t lre + t rae + t fwd ). settings of re and oe to the operation mode of read address pointer and data output. re oe internal read address pointer data output (latency 4) h h output h l incremented high impedance l h output l l halted high impedance power-up and initialization to assure proper operation of this me mory, place an interval of at least 200 s after vcc has stabilized to a value within the range of recommended opera ting conditions after power-up prior to the operation start. after this 200 s stabilization interval, the follo wing initialization sequence must be perfor med. because the read and write address pointers are undefined after power-up, a minimum of 150 dummy write operations (swck cycles) and read operations (srck cycles) must be performed, followed by an rstw operation and an rstr operation, to properly initialize the write and the read address pointer.
feds81v26000-02 oki semiconductor ms81v26000 11/20 new data read access in order to read out ?new data,? i.e., to read out data th at has been written in a follow-up manner, read reset must be input after write address 150 and the difference between the read address and the write address must be 350 or more but 1,114,111 or less. old data read access in order to read out ?old data,? i.e., to read out data that was written prior to the wr ite operation being carried out, the difference between the read address and the write address must be 0 or more but 30 or less. if the difference between the read address and the write address is between 31 and 349 or 1,114,112 or more, it is unpredictable whether the new data is output or whether the old data is output. in this case, however, the write data will be written normally.
feds81v26000-02 oki semiconductor ms81v26000 12/20 swck rstw di 0-23 t swc dn-3 we dn-2 d0 d1 t wswh t wswl t rstws t rstwh t ds t dh t lwe t fwd t wl t wae (=21clk):period of address input from write reset. a fter write reset, we should be remained high for 2 cycles after driving we high first. ie dn-1 dn 0 cycle 1 cycle wad wa0 wa1 wa2 w19 wa20 t wae t wans t wanh timing diagram write cycle timing (write reset)
feds81v26000-02 oki semiconductor ms81v26000 13/20 write cycle timing (write enable) write cycle timing (input enable) swck we di 0-23 d0 rstw d1 d6 d7 t wwel t wweh t wel 6 cycle 1 cycle 2 cycle 3 cycle 5 cycle 4 cycle d4 d5 d2 d3 t wens t wenh ?l? t wdss t wdsh 7 cycle ie ?h? swck ie di 0-23 d0 rstw d1 d10 d11 t wiel t wieh t iel 10 cycle 1 cycle 2 cycle 3 cycle 9 cycle 8 cycle d4 d5 d2 d3 t iens t ienh ?l? t idss t idsh 11 cycle we ?h? 6 cycle 5 cycle 4 cycle 7 cycle
feds81v26000-02 oki semiconductor ms81v26000 14/20 read cycle timing (read reset) srck rstr do 0-23 t src qn-3 re q0 q1 t wsrh t wsrl t rstrs t rstrh t lre t frd t rl t ac oe ?h? qn qn-2 qn-1 0 cycle 1 cycle rad ra0 ra1 ra2 ra19 ra20 t rae t rans t ranh t rae (=21clk): period of address input from read reset. a fter read reset, re should be remained high for 2 cycles after driving re high first.
feds81v26000-02 oki semiconductor ms81v26000 15/20 read cycle timing (read enable) read cycle timing (output enable) q5 srck re do 0-23 q0 rstr q1 q6 q7 t wrel t wreh t rel 6 cycle 1 cycle 2 cycle 3 cycle 5 cycle 4 cycle q2 t rens t renh ?l? t rdss t rdsh 7 cycle t ac oe ?h? q3 q4 srck oe do 0-23 q0 rstr q1 q10 q11 t woel t woeh t oel 10 cycle 1 cycle 2 cycle 3 cycle 9 cycle 8 cycle q2 t oens t oenh ?l? t odss t odsh 11 cycle t ac re ?h? q3 t deck t ddck 6 cycle 5 cycle 4 cycle 7 cycle q4 q5
feds81v26000-02 oki semiconductor ms81v26000 16/20 read / write cycle timing (new data read) swck rstw di 0-23 we t lwe t wae + t fwd n xn-3 xn-2 148 149 150 151 152 ie ?h? srck rstr do 0-23 re t lre t rae + t frd t rl n 0 1 2 3 oe ?h? 4 5 6 7 xn a0 a 1 a 2 a3 a 4 a 5 a 6 t ac read reset should be input after write address 150. a ddress difference is 350 or more and 1,114,111 or less. xn-1 xn t wl a0 a 1 0 1 2 the setting address for reading and that for writing are the same.
feds81v26000-02 oki semiconductor ms81v26000 17/20 read / write cycle timing (old data r ead) swck rstw di 0-23 we t lwe t wae + t fwd n bn-3 bn-2 ie ?h? srck rstr do 0-23 re t lre t rae + t frd t rl n 0 1 2 3 oe ?h? 4 xn b0 b1 b2 b3 b4 a ddress difference is 30 or less. bn-1 bn t wl a 0 a1 a 2 0 1 2 3 a 3 4 a 4 the setting address for reading and that for writing are the same.
feds81v26000-02 oki semiconductor ms81v26000 18/20 package dimensions notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humi dity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp100-p-1414-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.55 typ. 5 rev. no./last revised 4/oct. 28, 1996 (unit: mm)
feds81v26000-02 oki semiconductor ms81v26000 19/20 revision history page document no. date previous edition current edition description FEDS81V26000-01 may 14, 2004 ? ? final edition 1 FEDS81V26000-01 dec 15, 2004 20 20 p17 di0-23 xn ? bn
feds81v26000-02 oki semiconductor ms81v26000 20/20 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. wh en planning to use the product, please ensure that the external conditions are reflected in the act ual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accide nt, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual prop erty right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this docu ment are intended for use in genera l electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifi cally authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traf fic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2004 oki electric industry co., ltd.

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